This paper on "Encapsulation of TSOP 48L PEM from Design to Production" was presented at the NAFEMS World Congress on The Evolution of Product Simulation From Established Methods to Virtual Testing & Prototyping - 24-28 April 2001, The Grand Hotel, Lake Como, Italy.

Abstract

Due to this explosive growth in semiconductor market, the electronic packaging industry is faced with a challenge to deliver components in huge volumes at low cost and in a short time to market which in turn demands increase in capacity and reduction of cycle-time. Some of the key elements to be addressed are design for manufacturing, material and process development for automation and integration. Overall the targets were, keeping non-value steps like curing & handling to bare minimum, increased UPH at molding and strip testing to reduce test cycle time. To achieve these targets the biggest challenge was moldability of the leadframe configuration, which boasted 4 rows x 8 columns, mainly in view of strip testing.
This paper will discuss the challenges and issues the manufacturer and mold makers face in designing tools to encapsulate thin TSOP packages in such a large matrix configuration. It will address how CAE was applied to mold design, efforts with material vendors for the mold compound development and testing and experimental trials towards successful product development. The issues discussed are related to moldability such as wire sweep, voids and warpage. Experimental data will be presented to support the analysis results. An overview of how modeling and a good engineering judgment played their role in the overall success of the project is presented.