Abstract

Flash memory is widely used in computers, mobile devices and other electronic gadgets with the NAND logic gate based memory architecture commonly found in USB drives, memory cards and solid-state drives. NAND memory architecture offers higher storage density compared other memory architectures and were originally built as a 2D planar structure over the silicon wafer. To further improve the memory density, these 2D NAND structures were stacked on top of one another to create a complex 3D memory architecture. 3D NAND is the state of the art in flash memory technology and the number of stack layers exceeds 128 in many applications. Intro- ducing a higher number of film layers results in significant bowing of the silicon wafer substrate due to mismatch of thermal expansion coefficients between the different film layers within the stack combined with anisotropy introduced due to directional layout of devices on the wafer. Understanding and estimating the bowing of the substrate is crucial to successful execution of subsequent wafer processing steps like etching, deposition and lithography. A multi-scale modelling technique using a commercial finite element method (FEM) package is presented to estimate the wafer bow for 3D NAND applications. 3D NAND device structures on the wafer are periodic in nature at the micro-level. Three-dimensional representative volume element (RVE) method based on numerical homogenisation technique is used to estimate the effective material properties such as elastic constants and thermal expansion coefficients of these structures. The computed effective properties at the micro-level are mapped on to the die level that are at the meso-scale. The meso-scale consists of periodically patterned individual dies on the wafer with the necessary circuitries along with the 3D NAND devices. Two-dimensional RVE is employed at the meso-scale to estimate the effective elastic constants and thermal expansion coefficients of the dies. The macro bowing behaviour of the wafer is evaluated using the effective proper- ties computed at the micro and the meso scales. The bowing of the wafer along the bit-line and word-line directions are evaluated on cooling the wafer from a given process temperature to room temperature. Sensitivity studies are performed to understand the influence of various geometric and material properties of the given NAND structure on the overall macro behaviour of the wafer.